Flash memory is a type of semiconductor computer memory with many desirable characteristics. Like read only memory, ROM, it is non-volatile, meaning that the contents of the memory are stable and retained without applied electrical power.
Flash memory devices have found wide commercial success in the electronic device market. A major advantage of flash over ROM is that the memory contents of flash may be changed after the device is manufactured. Flash memory has found wide acceptance in many types of computers, including desktop computers, mobile phones and hand held computers. Flash memory is also widely used in digital cameras and portable digital music players, for example “MP3” players.
In addition to direct flash storage applications, for example in video cameras, flash-based storage devices are replacing rotating magnetic disks, sometimes known as hard drives, in many applications. Compared to hard drives, flash is significantly more rugged, quieter, lower power, and for some densities such a flash based device may be smaller than a comparable hard drive.
FIG. 1A shows a memory cell 10 as has been well known in the conventional art. Regions 14 are the drain and/or source regions for memory cell 10. They may be used as source and/or drain interchangeably. Control gate 16 is used to control the operation of memory cell 10. A channel region 17 is formed between source/drain regions 14. Feature size 18 is the nominal size of the smallest feature that can be created by a particular semiconductor process. In memory cells of this type, the gate 16 width and channel 17 length typically correspond approximately to feature size 18.
Memory cell 10 may be one of two general types of non-volatile memory, a “floating gate” cell or a nitride read only memory (NROM) cell. In a floating gate cell, layer 12B of the gate stack is typically conductive polysilicon. Layers 12A and 12C are insulating materials which isolate or “float” gate layer 12B, which is usually referred to as a floating gate. Floating gate 12B is the storage element of memory cell 10.
Silicon nitride based flash memory has many advantages as compared to its floating gate and tunneling oxide based counterparts. Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) is potentially very dense in terms of number of cells per unit area that can be used and it requires fewer process steps as compared to floating gate memory. Moreover, it can be easily integrated with standard SRAM process technology. A further advantage of using SONOS devices is their suitability for applications requiring large temperature variations and radiation hardening. The SONOS stack is a gate dielectric stack and consists of a single layer of polysilicon, a triple stack ONO (Oxide-Nitride-Oxide) gate dielectric layer and a MOS channel 17. The ONO structure may consist or a tunnel oxide 12A, a nitride memory storage layer 12B and a blocking oxide layer 12C.
Flash memory devices are typically configured as an array of many instanced of individual cells, e.g., cell 10, oriented in rows and columns. Typically, the control gates, e.g., control gate 16 of FIG. 1, of the cells in each row are connected to a series of word lines, thus forming individual rows of cells that can be accessed by selecting the corresponding word line. Similarly, the source and/or drain, e.g., regions 14, of the cells in each column are connected to a series of bit lines, thus forming individual columns of cells that can be accessed by selecting the corresponding bit lines.
Memory device manufacturers are continually challenged to provide ever greater amounts of memory at ever lower costs. Recently, Advanced Micro Devices, Incorporated of California has introduced MIRROR BIT™ nitride-based flash ROM that stores multiple bits per memory cell 10 physically separated in nitride layer 12B. Such storage of multiple bits per cell increases the storage density of the memory device, thereby reducing the cost per bit of storage.
To read a bit stored in the “left” portion of memory cell 10, a word line is brought to a read voltage of about 4.5 volts and a bit line is grounded. Node 14A (the “left” instance of regions 14) functions as a source for the cell, and current flows from node 14B, acting as a drain, to node 14A through a bit line to ground. Sensing logic connected to the bit line can interpret the magnitude of tie current (which is affected by the amount of charge stored in nitride gate layer 12B, in order to determine if a bit is stored in the “left” portion of cell 10.
To read a bit stored in the “right” portion of memory cell 10, a word line is brought to a read voltage of about 4.5 volts and a bit line is grounded. Node 14B (the “right” instance of regions 14) functions as a source for the cell, and current flows from node 14A, acting as a drain, to node 14B through a bit line to ground. Sensing logic connected to the bit line can interpret the magnitude of the current (which is affected by the amount of charge stored in nitride gate layer 12B, in order to determine if a bit is stored in the “right” portion of cell 10.
To write (or program) a bit into the “left” portion of memory cell 10, a line is brought to a programming voltage of about 9.5 volts, and a bit line is grounded and acts as a source. Current is sourced from the word line through node 14A into bit line. The current causes hot carrier injection of charge into the nitride layer of the SONOS stack in physical proximity to node 14A.
To write (or program) a bit into the “right” portion of memory cell 10, a line is brought to a programming voltage of about 9.5 volts, and a bit line is grounded and acts as a source. Current is sourced from the word line through node 14B into bit line. The current causes hot carrier injection of charge into the nitride layer of the SONOS stack in physical proximity to node 14B.
Another primary approach employed to achieve lower memory costs is the industry-wide on-going reduction in semiconductor feature size. By making features, such as signal lines and transistors smaller, more memory devices may be placed in a given die area, resulting in lower production costs.
However, as feature size 18 decreases to, for example, about 0.3 microns and smaller, the channel length also decreases. As channel length grows shorter, threshold voltage begins to decrease and leakage current increases. These effects are commonly referred to in the semiconductor arts as the “short channel effect.” An increase in leakage current is particularly onerous in flash memory devices as flash has found wide acceptance in very low power applications, for example mobile phones, due to the ability of flash to retain information without applied power. Increases in leakage current may have a significant deleterious effect on total power consumption of the flash device and the product using the flash device. Consequently, much research and development effort has gone into mitigating the short channel effect.
A conventional approach to mitigate the short channel effect is to have a non-uniform lateral (horizontal as depicted in FIG. 1) doping profile. Doping profile 20 illustrates such a non-uniform lateral doping profile. In the portion of channel region 17 near source/drain regions 14 the concentration of doping material is high, for example approximately in the range 1×1017˜5×1018 atoms/cm−3. In the “middle” of channel region 17, the concentration of doping material is lower than the doping concentration of a non-engineered channel. A laterally non-uniform channel is especially advantageous in compensating for channel length variations due to manufacturing process variability. If the channel length is increased, the length of the “middle” channel of low doping concentration is increased, which tends to keep the threshold voltage constant. Similarly, if the channel length is shortened, the “middle” channel is shortened, increasing the influence of the end regions of high doping concentration, which again tends to keep the threshold voltage constant.
The primary and conventional method of creating such a non-uniform lateral channel in MOS devices involves tilt angle implantation. A focused ion beam 25 generally containing one particle species (atom, molecule or atom cluster) is beamed into the semiconductor material. In order to implant the particles under a gate stack, e.g., layers 12A, 12B, 12C and 16, the beam is tilted at an angle “theta” 26 from the wafer normal. Doping may be conducted at several angles. By controlling numerous well known process variables, including e.g., dopant species, beam energy, angle(s) and time, a desired doping profile may be created in channel region 17.
Bulk memory integrated circuits comprise vast numbers of memory cells 10, placed as close together as possible in order to increase storage density and reduce costs. FIG. 1B illustrates three instances of memory cell 10 as a portion of a larger memory array. In addition to feature size 18 corresponding to gate width and channel width as described above, feature size 18 additionally nominally corresponds to the separation between instances of memory cell 10 within a larger array. Further, the gate structures of memory cells 10 extend in the third dimension, i.e., in and out of the drawing sheet.
Unfortunately, as feature size 18 decreases, (or example to 0.2 microns and smaller, tilt angle theta 26 becomes limited due to beam interference/obstruction with structures adjacent to the target, for example the gate stack of an adjacent memory cell. Consequently, in order to obtain the advantages of a non-uniform lateral channel, a new technique of constructing such a channel must be developed.
Semiconductor processing equipment is extremely expensive. Fundamental semiconductor processing steps, e.g., implantation and diffusion, typically require long periods of development and extensive qualification testing. Any solution to the short channel effect should be compatible with existing semiconductor processes and equipment without the need for revamping well established tools and techniques.
Thus a need exists to prevent short channel effects in dense arrays of memory cells. A further need exists for preventing short channel effects in a manner that is compatible and complimentary with conventional approaches to minimize short channel effects. A still further need exists for the above mentioned needs to be achieved with existing semiconductor processes and equipment without revamping well established tools and techniques.